The present invention relates to an information processing unit, and more particularly, to an information processing unit which manipulates a plurality of bits as the unit of processing information, such as 4-bit microprocessor, 8-bit microprocessor, etc.
The prior art information processing unit, for example 4-bit microprocessor, is constructed such that an input portion of a memory is connected to an output portion of a register by 4 bit signal lines, and an output portion of the memory is connected to an input portion of the register by 4 bit signal lines. Information is output, as 4-bit signals, from the memory by addressing and transferred to the register through the 4 bit signal lines to be set therein, simultaneously, and vice versa. In this event, the register consists of a 4-bit latch circuit (four flip-flop circuits). However, the information processing unit includes such circuits that manipulate information consisting of more than 4 bits, e.g., 8 bits. Examples of such circuits are a counter circuit, an accumulator circuit and two registers for loading two bytes of data. They are 8-bit processing circuits in which 8-bits of information are simultaneously manipulated. Input and output portions of these circuits should be connected to 4-bit processing circuits (for example, the above-mentioned memory) via 4-bit signal lines. Therefore, in the prior art information unit, the 8-bit information must be divided into two groups of 4-bit information, each transferred sequentially between the memory and the 8-bit processing circuits. Therefore, transfer is required twice and execution of a transferring instruction has to be repeated by spending at least two machine cycles in order to transfer the 8-bit information. As a result, information transferring speed is very slow in the prior art 4-bit microprocessor. There is a similar disadvantage in the 8-bit microprocessor necessitating 16-bit manipulation.
On the other hand, as the memory in the 4-bit microprocessor is designed such that 4 bits of information are simultaneously written in and/or read out by one memory accessing with one memory address, it is impossible to write in and/or read out 8 bits of information in parallel to and/or from the memory. Namely, in the prior art 4-bit microprocessor the number of signal lines is equal to the minimum unit of processing information (4 bits), and especially the number of signal lines for information transferring depends on the number of memory information accessed by one addressing. Such problems also arise in other information processing units which manipulate more than 4 bits of information as the unit of processing information.
Moreover, where an information processing unit is controlled by instructions with variable bit length (for example one byte instruction, two bytes instruction, three bytes instruction, etc.), accessing and transferring time for the instruction is very long because of the necessity of a plurality of memory accesses. For instance, three addressing sequences are required to read out a three byte instruction from a memory, that is, at least three machine cycles are spent for a memory access operation. As a result, not only does the processing speed become low, but also programming for memory access becomes complex.